1. Field of the Invention
The present invention relates to a programmable logic device (PLD) and, more particularly, to an arrangement of a programmable logic array (PLA) comprising a programmable AND array performing a logical "and" operation, a programmable OR array performing a logical "or" operation, and the associated drive-, output- and feedback-circuits.
Note, in the following description, a mode in which a normal operation of the PLD, i.e., a normal logical operation of the "and" operation and "or" operation, is carried out will be referred to hereinafter as a normal mode. Also, a mode in which data is written into the cell array and then a verification of whether or not the data is correctly written is carried out, will be referred to hereinafter as a program mode.
2. Description of the Related Art
FIG. 1 illustrates a circuit constitution of a known PLA, as disclosed in U.S. Pat. No. 4,041,459. In FIG. 1, reference 1 denotes an AND array or matrix and reference 2 denotes an OR array or matrix. References 6 and 7 denote buffers, each including a complementary metal oxide semiconductor (CMOS) inverter composed of transistors 61 and 62, which are connected between the AND array 1 and the OR array 2, reference 4 denotes a decoder arrangement functioning as a data input/output (I/O) buffer, and reference 5 denotes a decoder. The data I/O buffer 4 and decoder 5 are provided for each of the AND array 1 and OR array 2.
In the program mode, data is written into the cell array by the data I/O buffer 4 and decoder 5 and then a verification of whether or not the data is correctly written is carried out by the corresponding data I/O buffer 4. The above verification will be referred to hereinafter as a program verify. For example, where data is written into the OR array, control lines, i.e., product term lines P.sub.l '.about.P.sub.n ', are driven to high voltage higher than a voltage normally employed in the read operation. Accordingly, to prevent the high voltage present at the product term lines from exerting an influence on the AND array side, the buffers 6 and 7 are brought to a floating state, i.e., a disable state. At the same time, a diode 63 reversely inserted between the CMOS inverter 61, 62 and a power supply line U.sub.DD in the buffer 6 prevents a current flow from the product term lines P.sub.l '.about.P.sub.n ' toward the power supply line.
Namely, according to the constitution of the PLA shown in FIG. 1, the buffers 6 and 7 are disabled in the program mode, resulting in a separation of the AND array add the OR array. In other words, the AND array and OR array are not electrically associated in the program mode.
Therefore, when data is written into the AND array and the written data is then read out through the OR array, a problem occurs. Namely, since the buffers 6 and 7 are disabled and the AND array and the OR array are not electrically associated, the buffers 6 and 7 must be enabled to read out the data written into the AND array through the OR array. At the same time, it must be verified whether or not the buffers are functional, by employing "another means", which will be referred to hereinafter as a logic verify. But a large amount of test pattern data must be employed for the verification, and the logic verify must be carried out, and therefore, when data is written into the AND array and the logic verify of the data is then carried out, the processing is made remarkably complicated and cumbersome, which is not preferable from the viewpoint of the efficiency of the verify/check operation.
Note, in the following description, the term verify-check implies both a program verify and a logic verify.